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this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice april 2014 docid025943 rev 2 1/53 STW81200 multi-band rf fractional/int eger frequency synthesizer with integrated vcos datasheet - preliminary data features ? output frequency range: 46.875 to 6000 mhz ? very low noise ? normalized in band phase noise floor: -227 dbc/hz ? vco phase noise: -135 dbc/hz @ 1 mhz offset, 4.0 ghz carrier ? noise floor: -160 dbc/hz ? dual architecture frequency synthesizer: fractional-n and integer-n ? integrated vcos with automatic center frequency calibration ? programmable rf output dividers by 1/2/4/8/16/32/64 ? dual rf output broadband matched with programmable power level and mute function ? external vco option with 5 v charge pump ? integrated low noise ldo voltage regulators ? maximum phase detector frequency: 100 mhz ? exact frequency mode ? fast lock and cycle slip reduction ? differential reference clock input (lvds and lvecpl compliant) supporting up to 800 mhz ? 13-bit programmable reference frequency divider ? programmable charge pump current ? digital lock detector ? integrated reference crystal oscillator core ? r/w spi interface ? logic compatibility/to lerance 1.8 v/3.3 v ? low power functional mode ? supply voltage: 3.0 v to 5.4 v ? small size exposed pad vfqfpn36 package ? 6 x 6 x 1.0 mm ? process: bicmos 0.25 m sige applications ? cellular/4g infrastr ucture equipment ? instrumentation and test equipment ? cable tv ? other wireless communication systems description the STW81200 is a dual architecture frequency synthesizer (fractional-n and integer- n), that features three low phase noise vcos with a fundamental frequency range of 3.0 ghz to 6.0 ghz and a programmable dual rf output divider stage which allows to cover from 46.875 mhz to 6 ghz. the STW81200 optimizes size and cost of the final application thanks to the integration of low noise ldo voltage regulators and internally broadband matched rf outputs. the STW81200 is compatible with a wide range of supply voltage (from 3.0 v to 5.4 v) providing to the end user a very high level of flexibility which trades off excellent performance with power dissipation requirements. a low power functional mode (software-controlled) gives an extra power saving. additional features includ e crystal oscillator core, external vco mode and output mute function. vfqfpn36 table 1. device summary order code package packing STW81200t vfqfpn36 tray STW81200tr vfqfpn36 tape and reel www.st.com
contents STW81200 2/53 docid025943 rev 2 contents 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 typical performance characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 pll n divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 phase frequency detector (pfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.7 fast lock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 cycle slip reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.9 voltage controlled oscillators (vcos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.10 rf output divider stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.11 low power functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.12 STW81200 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.13 STW81200 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.14 power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.15 example of register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
docid025943 rev 2 3/53 STW81200 list of figures 3 list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. vco open loop phase noise @ 5 v supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. closed loop phase noise at 4.8 ghz, divided by 1 to 64 (5 v supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. vco open loop phase noise at 4.4 ghz vs. supply setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. vco open loop phase noise over frequency ghz vs. supply setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. single sideband integrated phase noise (5 v supply; fpfd=50mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. output power level ? single ended (3 db more for differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. phase noise and fractional spurs at 2646.96 mhz vs supply setup (fpfd=61.44 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. phase noise and fractional spurs at 2118.24 mhz vs supply setup (fpfd=61.44 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. phase noise and fractional spurs at 2118.24 mhz at 5.0 v supply (fpfd=61.44 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. phase noise and fractional spurs at 2118.24 mhz at 3.6 v supply (fpfd=61.44 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. phase noise and fractional spurs at 2118.24 mhz at 3.0 v supply (fpfd=61.44 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. phase noise at 5.625 ghz and 4.6 ghz (fpfd=50 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15. typical vco control voltage after vco calibration @ 3.6 v supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. figure of merit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. reference clock buffer configurations: singl e-ended (a), differential (b), crystal mode (c) 22 figure 18. pfd diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19. spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 20. spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 21. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 22. application diagram (external vco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 23. package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
list of tables STW81200 4/53 docid025943 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. phase noise specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. current value vs. selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. blocks with programmable current and related perf ormance . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. spi timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11. spi register map (address 12 to 15 not available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
docid025943 rev 2 5/53 STW81200 functional block diagram 52 1 functional block diagram figure 1. functional block diagram
pin definitions STW81200 6/53 docid025943 rev 2 2 pin definitions figure 2. top view vin_ldo_4v5 cbyp_4v5 1 vreg_4v5 2 vcc_vco_core 3 hw_pd 4 pdrf1 5 pdrf2/fl_sw 6 cbyp 7 36 test_se 35 rf2_outp 34 rf2_outn 33 vcc_rfout 32 rf1_outp 31 rf1_outn 30 27 26 25 24 23 22 21 10 11 12 13 14 15 16 vreg_dig vdd_dsm_ndiv le sck sdi ld_sdo ref_clkp vr vctrl extvco_inp extvco_inn vdd_cp icp vcc_cpout 8 9 vreg_vco vin_ldo_vco vreg_rf 29 vin_ldo_rf_dig 28 17 18 vdd_pfd vin_ldo_ref 20 19 ref_clkn vreg_ref
docid025943 rev 2 7/53 STW81200 pin definitions 52 table 2. pin description pin no name description observation 1 cbyp_4v5 connection for 4.5 v regulator bypass capacitor - 2vreg_4v5 regulated output voltage for 4.5v regulator adjustable output voltage: 5.0 v, 4.5 v, 2.6 v, 3.3 v 3 vcc_vco_core supply voltage for vco core it must be connected to vreg_4v5 or vreg_vco 4 hw_pd hw power down cmos schmitt triggered input, 1.8 v compatible, 3.3 v tolerant 5 pd_rf1 rf1 output stage power down control cmos schmitt triggered input, 1.8 v compatible, 3.3 v tolerant 6 pd_rf2/fl_sw rf2 output stage power down control / fast lock switch cmos schmitt triggered input, 1.8 v compatible, 3.3v tolerant (with fast lock feature disabled); high impedance/ gnd shorted output (with fast lock feature enabled) 7 cbyp connection for vco circuitry regulator bypass capacitor - 8vreg_vco regulated output voltage for vco circuitry regulator - 9 vin_ldo_vco supply voltage for vco circuitry regulator - 10 vr connection for reference voltage filtering capacitor - 11 vctrl vco co ntrol voltage - 12 extvco_inp external vco positive input it must be connected to ground if external vco is not used 13 extvco_inn external vco negative input it must be connected to ground if external vco is not used 14 vcc_cp_bias supply voltage for charge pump bias it must be connected to vreg_vco 15 icp pll charge pump output - 16 vcc_cpout supply voltage for charge pump output stage it must be connected to vreg_4v5 or vreg_vco 17 vdd_pfd supply voltage for pfd it must be connected to vreg_ref 18 vin_ldo_ref supply voltage for pll regulator - 19 vreg_ref regulated output voltage for reference clock regulator - 20 ref_clkn reference clock negative input - 21 ref_clkp reference clock positive input -
pin definitions STW81200 8/53 docid025943 rev 2 22 ld_sdo lock detector/spi data output cmos push-pull output 2.5v with slew rate control or open drain (1.8v to 3.3v tolerant) 23 sdi spi data input cmos schmitt triggered input, 1.8 v compatible, 3.3 v tolerant 24 sck spi clock cmos schmitt triggered input, 1.8 v compatible, 3.3 v tolerant 25 le spi load enable cmos schmitt triggered input, 1.8 v compatible, 3.3 v tolerant 26 vdd_dsm_ndiv supply voltage for dsm and n divider it must be connected to vreg_dig 27 vreg_dig regulated output voltage for digital circuitry regulator - 28 vin_ldo_rf_dig supply voltage for rf output divider stage and digital regulators - 29 vreg_rf regulated output voltage for rf output divider stage regulator - 30 rf1_outn main rf negative output 50 output impedance 31 rf1_outp main rf positive output 50 output impedance 32 vcc_rfout supply voltage for rf output stages connected to vreg_div, vreg_4v5 or external 5v 33 rf2_outn auxiliary rf negative output 50 output impedance 34 rf2_outp auxiliary rf positive output 50 output impedance 35 test_se test pin it must be connected to ground 36 vin_ldo_4v5 supply voltage for 4.5 v regulator - table 2. pin description (continued) pin no name description observation
docid025943 rev 2 9/53 STW81200 absolute maximum ratings 52 3 absolute maximum ratings table 3. absolute maximum ratings symbol parameter value unit vcc supply voltage pins #14, #17, #26 -0.3 to 2.7 v supply voltage ldos pins #9, #18, #28, #36 -0.3 to 5.4 v supply voltage pins #3 -0.3 to 5 v supply voltage pins #16, #32 -0.3 to 5.4 v tstg storage temperature +150 c esd electrical static discharge hbm cdm-jedec standard mm 2 0.5 0.2 kv
operating conditions STW81200 10/53 docid025943 rev 2 4 operating conditions table 4. operating conditions symbol parameter test conditions min typ max unit vcc supply voltage pins #14, #17, #26 - 2.5 - 2.7 v supply voltage (ldos inputs) pins #9, #18, #28, #36 - 3.0 - 5.4 v supply voltage pin #3, #16, #32 - 2.5 - 5 v i cc current consumption pin #3, #16 and #32 supplied at 4.5 v div2 on, main output only, 4 ghz vco, max. performance -84-ma current consumption pin #3, #16 and #32 supplied at 2.6 v -50-ma current consumption other blocks an supplies at 2.6 v -110-ma t a operating ambient temperature - -40 - 85 c t j maximum junction temperature - - - 125 c ja junction to ambient package thermal resistance (1) multilayer jedec board - 33 - c/w jb junction to board package thermal resistance (1) multilayer jedec board - 18 - c/w jc junction to case package thermal resistance (1) multilayer jedec board - 3 - c/w jb thermal characterization parameter junction to board (1) multilayer jedec board - 17 - c/w jt thermal characterization parameter junction to top case (1) multilayer jedec board - 0.3 - c/w 1. refer to jedec standard jesd 51-12 for a detailed description of the thermal resistances and thermal parameters. data here presented are referring to a multilayer board according to jedec standard. t j = t a + j a * p diss (in order to estimate t j if ambient temperature t a and dissipated power p diss are known) tj = t b + jb * p diss (in order to estimate t j if ambient temperature t b and dissipated power p diss are known) t j = t t + jt * p diss (in order to estimate t j if ambient temperature t t and dissipated power p diss are known)
docid025943 rev 2 11/53 STW81200 operating conditions 52 table 5. digita l logic levels symbol parameter test conditions min typ max unit vdd internal supply for digital circuits - - 2.6 - v vil low level input voltage schmitt input 0 - 0.6 v vih high level input voltage schmitt input 1.2 - 3.6 v vol low level output voltage - - - 0.2 v voh high level output voltage - vdd-0.2 - - v
electrical specifications STW81200 12/53 docid025943 rev 2 5 electrical specifications all electrical specifications are given at 25 o c t amb and in a full-cu rrent mode, unless otherwise stated. table 6. electrical specifications symbol parameter condition min typ max units output frequency range f out output frequency direct output 3000 - 6000 mhz divider by 2 output 1500 - 3000 mhz ??-?mhz divider by 64 output 46.875 - 93.75 mhz vco dividers n vco divider ratio integer mode 24 - 131071 - fractional mode (dsm 1 st order) 24 - 510 - fractional mode (dsm 2 nd order) 25 - 509 - fractional mode (dsm 3 rd order) 27 - 507 - fractional mode (dsm 4 st order) 31 - 503 - xtal oscillator f xtal xtal frequency range - 10 - 50 mhz esr xtal xtal esr - - - 50 ? p xtal xtal power dissipation - - - 5 mw cin xtal xtal oscillator input capacitance single ended 0.6 - - pf pn xtal xtal oscillator phase noise floor 50 mhz xtal - -162 - dbc/hz tol xtal xtal oscillator accuracy @12 mhz, 25 oc - - 10 ppm reference clock and phase frequency detector f ref reference input frequency (1) -10-800mhz reference input sensitivity differential mode 0.2 1 1.25 vp single ended mode 0.35 1 1.25 vp pn refin reference input buffer phase noise floor single ended mode @100 mhz, sinusoidal signal 1.25 vp - -163 - dbc/hz lvds signal @100 mhz 400 mvp - -159 - dbc/hz
docid025943 rev 2 13/53 STW81200 electrical specifications 52 i ref current consumption (2) differential mode - 10 - ma single ended mode - 3 - xtal oscillator mode - 5 - r reference divider ratio - 1 - 8191 f pfd pfd input frequency (3) ---100mhz f step frequency step (3) lo direct output 47.5 hz lo with divider by 2 23.75 hz ??hz lo with divider by 64 0.7422 hz charge pump vcc cpout cp supply pin # 16 (vcc_cpout) 2.5 - 5 v i cp icp sink/source 5-bit programmable - - 4.9 ma v ocp output voltage compliance range -0.4- vcc cpout -0.4 v comparison frequency spurs (4) ---85 dbc in-band fractional spurs (5) ---50 vcos vcc vcocore vco core supply pin # 3 (vcc_vco_core) 2.5 - 5 v i vcocore oscillator core current consumption @ 4 ghz and 4.5 v supply - 52 - ma @ 4 ghz and 3.3 v supply - 35 - @ 4 ghz and 2.6 v supply - 30 - i vcobuf vco buffer consumption pin # 3 (vcc_vco_core) - 35 - ma k vco vco gain vco freq. range: 3.0 to 4.0 ghz - 35-85 - mhz/v vco freq. range: 4.0 to 5.0 ghz - 40-90 - mhz/v vco freq. range: 5.0 to 6.0 ghz - 45-95 - mhz/v t lk maximum temperature variation for continuous lock (6)(7) pin #16 @4.5/5 v -125 125 o c pin #16 @3.3 v -125 125 o c pin #16 @2.6 v -125 115 o c rf output stage vcc rfout rf output supply pin # 35 (vcc_rfout) 2.5 - 5 v p out output level differential 3.3 v to 5 v supply -1 - +7 dbm - differential 2.6 v supply -1 - +1 table 6. electrical specifications (continued) symbol parameter condition min typ max units
electrical specifications STW81200 14/53 docid025943 rev 2 z out output impedance differential - 100 - ? single ended - 50 - ? r l return loss matched to 50-ohm single ended -15 -db h 2 lo 2 nd harmonic direct output (single/di fferential) - -30/-40 - dbc divided output (single/differential) - -30/-35 - dbc h 3 lo 3 rd harmonic direct output (single/di fferential) - -15/-15 - dbc divided output (single/differential) - -15/-15 - dbc p mute level of signal with rf mute enabled direct output @4 ghz (single/diff) - -45/-60 - dbm divided output @2 ghz (single/diff) - -45/-60 - dbm p iso main/aux port isolation direct output @4 ghz (single/diff) - -35/-40 - dbc divided output @2 ghz (single/diff) - -40/-45 - dbc i div rf divider current consumption (8) direct output (1 differential output) -28 - ma div2 buff (1 differential output) - 47 - div4 buff (1 differential output) - 56 - div8 buff (1 differential output) - 65 - div16 buff (1 differential output) - 75 - div32 buff (1 differential output) - 83 div64 buff (1 differential output) - 92 - auxiliary path enabled - 19 - i rfoutbuf rf output buffer current consumption (8) 3.3 v to 5 v supply (1 differential output; p out = +7 dbm) -25 - ma 3.3 v to 5 v auxiliary path enabled -25 - 2.6 v supply (1 differential output; p out = +1 dbm) -12 - 2.6 v auxiliary path enabled - 12 - table 6. electrical specifications (continued) symbol parameter condition min typ max units
docid025943 rev 2 15/53 STW81200 electrical specifications 52 pll miscellaneous i pll pll current consumption (8) prescaler, digital dividers, misc. - 20 - ma i dsm ? modulator current consumption (8) --3.5-ma 1. the maximum frequency of the reference divider is 200 mhz; when using higher reference clock frequency (up to the max. value of 800 mhz) the internal divider by 2 or divider by 4 must be enabled. the fractional mode is allowed in the full frequency range only with reference clock frequency >11.93 mhz with reference clock frequency in the range 10 mhz to 11 .93 mhz, due to the limits of n value in fractional mode, the full vco frequencies would not be addressed in fractional mode; in this case the frequency doubler in the reference path can be enabled. 2. reference clock signal @ 100 mhz, r=2 3. the minimum frequency step is obtained as f pfd / (2^21); these typical values are obtained considering f pfd = 100 mhz. 4. pfd frequency leakage. 5. this is the level inside the pll loop bandwidth due to the contribution of the ? modulator. in order to obtain the fractional spurs level for a specific frequency offset , the attenuation provided by the loop filter at such offset should be subtracted. 6. once a vco is programmed at the initial temperature t 0 inside the operating temperature range (-40 c to +85 c), the synthesizer is able to maintain the lock status only if the temperature drift (in either direction) is within the limit specified by t lk , provided that the final temperature t f is still inside the nominal range. 7. in order to guarantee the performance of t lk the bit cal_temp_comp in register st6 must be set to ?1?. 8. current consumption measured with pll locked in foll owing conditions: reference clock signal @ 100 mhz; pfd @50 mhz (r=2); vco @ 4005 mhz table 6. electrical specifications (continued) symbol parameter condition min typ max units
electrical specifications STW81200 16/53 docid025943 rev 2 table 7. phase noise specifications (1) parameter min typ max units normalized in band phase noise floor (2) --227-dbc/hz vco open loop phase noise at f out @ 4 ghz ? vin=5.0 v, vreg=4.5 v phase noise @ 1 khz - -64 - dbc/hz phase noise @ 10 khz - -91 - dbc/hz phase noise @ 100 khz - -114 - dbc/hz phase noise @ 1 mhz - -135 - dbc/hz phase noise @ 10 mhz - -154 - dbc/hz phase noise @ 100 mhz - -160 - dbc/hz vco open loop phase noise at f out @ 4 ghz/2 = 2ghz ? vin=5.0 v, vreg=4.5 v phase noise @ 1 khz - -70 - dbc/hz phase noise @ 10 khz - -97 - dbc/hz phase noise @ 100 khz - -120 - dbc/hz phase noise @ 1 mhz - -141 - dbc/hz phase noise @ 10 mhz - -156 - dbc/hz phase noise @ 40 mhz - -159 - dbc/hz vco open loop phase noise at f out @ 4 ghz/4 = 1 ghz ? vin=5.0 v, vreg=4.5 v phase noise @ 1 khz - -76 - dbc/hz phase noise @ 10 khz - -103 - dbc/hz phase noise @ 100 khz - -126 - dbc/hz phase noise @ 1 mhz - -146 - dbc/hz phase noise @ 10 mhz - -159 - dbc/hz phase noise floor - -160 - dbc/hz vco open loop phase noise at f out @ 4 ghz/32 = 125 mhz ? vin=5.0 v, vreg=4.5 v phase noise @ 1 khz - -92 - dbc/hz phase noise @ 10 khz - -121 - dbc/hz phase noise @ 100 khz - -144 - dbc/hz phase noise @ 1 mhz - -161 - dbc/hz phase noise @ 10 mhz - -163 - dbc/hz phase noise floor - -164 - dbc/hz vco open loop phase noise at f out @ 4 ghz ? vin=3.6v , vreg=3.3 v phase noise @ 1 khz - -62 - dbc/hz phase noise @ 10 khz - -89 - dbc/hz phase noise @ 100 khz - -113.2 - dbc/hz
docid025943 rev 2 17/53 STW81200 electrical specifications 52 phase noise @ 1 mhz - -133.6 - dbc/hz phase noise @ 10 mhz - -152.4 - dbc/hz phase noise @ 100 mhz - -158.5 - dbc/hz vco open loop phase noise at f out @ 4 ghz ? vin=3.0 v, vreg=2.6 v phase noise @ 1 khz - -60.5 - dbc/hz phase noise @ 10 khz - -88 - dbc/hz phase noise @ 100 khz - -110.3 - dbc/hz phase noise @ 1 mhz - -131 - dbc/hz phase noise @ 10 mhz - -150 - dbc/hz phase noise @ 100 mhz - -157 - dbc/hz 1. phase noise ssb unless otherwise s pecified. the vco open loop figures are spec ified at 4.5/5 v on vcc_vco_core (pin #3). 2. normalized pn = measured pn ? 20log(n) ? 10log(f pfd ) where n is the vco divider ratio and f pfd is the comparison frequency at the pfd input. table 7. phase noise specifications (1) parameter min typ max units
typical performance characteristics STW81200 18/53 docid025943 rev 2 6 typical performance characteristics figure 3. vco open loop phase noise @ 5 v supply figure 4. closed loop phase noise at 4.8 ghz, divided by 1 to 64 (5 v supply) figure 5. vco open loop phase noise at 4.4 ghz vs. supply setup figure 6. vco open loop phase noise over frequency ghz vs. supply setup
docid025943 rev 2 19/53 STW81200 typical performance characteristics 52 figure 7. single sideband integrated phase noise (5 v supply; fpfd=50mhz) figure 8. output power level ? single ended (3 db more for differential) figure 9. phase noise and fractional spurs at 2646.96 mhz vs supply setup (f pfd =61.44 mhz) figure 10. phase noise and fractional spurs at 2118.24 mhz vs supply setup (f pfd =61.44 mhz)
typical performance characteristics STW81200 20/53 docid025943 rev 2 figure 11. phase noise and fractional spurs at 2118.24 mhz at 5.0 v supply (f pfd =61.44 mhz) figure 12. phase noise and fractional spurs at 2118.24 mhz at 3.6 v supply (f pfd =61.44 mhz) figure 13. phase noise and fractional spurs at 2118.24 mhz at 3.0 v supply (f pfd =61.44 mhz) figure 14. phase noise at 5.625 ghz and 4.6 ghz (f pfd =50 mhz)
docid025943 rev 2 21/53 STW81200 typical performance characteristics 52 figure 15. typical vco control voltage after vco calibration @ 3.6 v supply figure 16. figure of merit
circuit description STW81200 22/53 docid025943 rev 2 7 circuit description 7.1 reference input stage the reference input stage provides different modes for the reference clock signal. both single-ended and differential modes (lvds, lvecpl) are supported; a crystal mode is also provided in order to build a pierce type crystal oscillator. figure 17 shows the connections required for the diff erent configurations supported. in single-ended and differential modes the i nputs must be ac coupled as the ref_clkp and ref_clkn pins are internally biased to an optimal dc operating point. the input resistance is 100 ohms differential and the best performance for phase noise is obtained for signals with a higher slew rate, such as a square wave. figure 17. reference clock buffer configurations: single-ended (a), differential (b), crystal mode (c) 7.2 reference divider the 13-bit programmable reference counter is used to divde the input reference frequency to the desired pfd frequency. the division ratio is programmable from 1 to 8191. the maximum allowed input frequency of the r-counter is 200 mhz. the reference clock can be extended up to 400 mhz enabling the divide-by-2 stage or up to 800 mhz enabling the divide-by-4 stage. a frequency doubler is provided in order to double low reference frequencies and increase the pfd operating frequency thus allowing an easi er filtering of the out-of-band noise of the delta-sigma modulator; the doubler is introducing a noise degradation in the in-band pll noise thus this feature should be carefully used. when the doubler is enabled, the maximum reference frequency is limited to 25 mhz. ref_clkp ref_clkn ref_clkp ref_clkn ref_clkp ref_clkn 100 a) b) c)
docid025943 rev 2 23/53 STW81200 circuit description 52 7.3 pll n divider the n divider set the division ratio in the pll feedback path. both integer-n and fractional-n pll architectures are implemented in order to ensure the best overall performance of the synthesizer. the fractional-n division is achieved combin ing the integer divider section with a delta- sigma modulator (dsm) which sets the fracti onal part of the overall division ratio. the dsm is implemented as a mash structure with programmable order (2 bit; 1 st , 2 nd , 3 rd and 4 th order), programmable modulus (21 bit). it includes also a dithering function (1 bit) which can be used to reduce fractional spur tones by spreading the dsm sequence and cons equently the energy of the spurs over a wider bandwidth. the overall divisio ratio n is given by: the integer part n int is 17-bit programmable and can range from 24 to 131071 in integer mode. for n int 512 the fractional mode is not allo wed and the setting used for dsm does not have any effect. based upon the selected order of the delta-sigma modulator the allowed range of n int values changes as follows: ? 24 to 510 - 1st order dsm ? 25 to 509 - 2nd order dsm ? 27 to 507 - 3rd order dsm ? 31 to 503 - 4th order dsm the fractional part n frac of the division ratio is controlle d by setting the values frac and mod (21 bits each) and it depends also on the value of dithering (1 bit): the mod value can range from 2 to 2097151, while the range of frac is from 0 to mod-1. if the dithering function is not used (dithe ring=0) the fractional part of n is simply achieved as ratio of frac over mod. nn int n frac + = n frac frac mod ---------------- - dithering 2mod ? ----------------------------------- + =
circuit description STW81200 24/53 docid025943 rev 2 the resulting vco frequency is: where: f vco is the output frequency of vco f ref is the input reference frequency r is the division ratio of reference chain n is the overall division ratio of the pll the implementation with programmable modulus a llows the user to select easily the desired fraction and the exact synthesized frequency whitout any approximation. the mod value can be set to very high values thus the frequency resolution of the synthesizer can reach very fine steps (down to a few hertz). a ?low spur mode? could be configured by ma ximizing both frac and mod values, keeping the same desired frac/mod ratio, and setting the dithering bit to ?1?. the drawback is a small frequency error, equal to f pfd /(2*mod), on the synthesized frequency which is in the range of a few hertz, usually tolerated by most applications. 7.4 phase frequenc y detector (pfd) the pfd takes inputs from the reference and the vco dividers and produces an output proportional to the phase error. the pfd includes a delay gate that cont rols the width of the anti-backlash pulse (1.2 to 3 ns). this pulse ensures that there is no dead zone in the pfd transfer function. the following figure is a simplified schematic of the pfd. f vco f ref r --------- - n ? f ref r --------- - n int frac mod ---------------- - dithering 2mod ? ----------------------------------- ++ ?? ?? ? ==
docid025943 rev 2 25/53 STW81200 circuit description 52 figure 18. pfd diagram 7.5 lock detect the lock detector indicates the lock state for the pll. the lock condition is detected by comparing the up and down outputs of the digital phase frequency detector a cmos logic output signal indicates the lock st ate; the polarity of th e output signal can be inverted using the ld_activelow bit. the lock condition occurs when the delay betw een the edges of up and down signals is lower than a specific value (3-bit programmabl e from 2 ns to 16 ns) and this condition is stable for a specific number of consecutive pfd cycles (3-bit programmable counter from 4 to 4096 cycles). this flexibility is needed by the lock detector ci rcuitry to work properly with all the possible different pll setups (integer-n, fractional-n, different pfd frequencies and so on). 7.6 charge pump this charge pump consists of two matched current sources, iup and idown, which are controlled respectively by up and down pfd outputs. the nominal value of the output current (i cp ) is controlled by the selection among 32 different values by a 5-bit word. the minimum value of the output current (i cp ) is 158 a. the charge pump also includes a compensation circuitry to take into account the k vco variation with the loop filter vco control voltage. it adjusts the nominal i cp value, minimizing the variation of the product of i cp and k vco to keep the pll bandwidth constant. the charge pump output stage can be supplied from 2.5 v to 5.0 v. up down abl delay dff r r dff vdd fref fref vdd
circuit description STW81200 26/53 docid025943 rev 2 7.7 fast lock mode the fast-lock feature can be enabled to trad e fast settling time wi th spurs rejection, performances which are generally requiring diff erent settings of pll bandwidth (narrow for better spurs rejection and wide for fast settling time). a narrow bandwidth for lower spurs can be designed for the lock state while a wider bandwidth can be designed for the pll transients. the wider bandwidth is achieved during the tran sient by increasing the charge pump current and reducing accordingly the dumping resistor valu e of the loop filter in order to keep the phase margin of the pll constant. the duration of the pll wide band mode, in terms of number of pfd cycles, is set by programming the fast lock 13 bit counter. 7.8 cycle slip reduction the use of high f pfd /pll_bw ratios may lead to an increased settling time due to cycle slips. a cycle slip compensation circuit is provid ed which automatically increases the charge pump current for high frequency errors and re stores the programmed value at the end of the locking phase. 7.9 voltage controlled oscillators (vcos) the STW81200 vco section consists of three separate low-noise vcos with different lc tanks structures to cover a wide band from 3000 mhz to 6000 mhz. each vco is implemented using a structure wi th multiple sub-bands to keep low the vco sensitivity (kvco), thus resulting in low phase noise and spurs performances. the correct vco and sub-band selection is au tomatically performed by a dedicated digital circuitry (clocked by the pfd) at every new frequency programming. during the selection procedure the vctrl of the vco is charged to a fixed reference voltage. table 8. current value vs. selection cpsel4 cpsel3 cpsel2 cpsel1 cpsel0 current value 00000- 0 00001i min 158 a 000102*i min 316 a ------ - ------ - 1110129*i min 4.58 ma 1111030*i min 4.74 ma 1111131*i min 4.9 ma
docid025943 rev 2 27/53 STW81200 circuit description 52 the procedure for the vco and sub-band selection takes approximately 11 * caldiv pfd cycles, where caldiv is the division ratio of the programmable divider included in the path between the pfd and the selection circuitry. the maximum frequency allowed for the sub- band selection is 1mhz and the caldiv value must be set accordingly if the pfd frequency is higher. once the correct vco and sub-band are selected the normal pll operations are resumed. the vco core could be supplied up to 5 v for maximum performance or to a minimum of 2.5 v trading off current consumption and performance. 7.10 rf output divider stage the signal coming from the vcos is fed to a flexible rf divider stage. the divider ratio is programmable among differen t values (1, 2, 4, 8 ,16, 32 and 64) and allows the selection of the desired output frequency band: ? 3.0 to 6.0 ghz (divider ratio = 1) ? 1.5 to 3.0 ghz (divider ratio = 2) ? 0.75 to 1.5 ghz (divider ratio = 4) ? 375 to 750 mhz (divider ratio = 8) ? 187.5 to 375 mhz (divider ratio = 16) ? 93.75 to 187.5 mhz (divider ratio = 32) ? 46.875 to 93.75 mhz (divider ratio = 64) the final output stage buffer (pins rf1_outp, rf1_outn) is internally broadband matched to 100-ohm differential (50-ohm single-ended) and it delivers up to +7 dbm of output power on a 100-ohm differential load (+4 dbm on 50-ohm from each single-ended output). the final output stage buffer has a 3-bit programmable output level and can be powered down by software and/or hardware (pin pd_rf1) while the internal pll is locked. an auxiliary output stage buffer (pins rf 2_outp and rf2_outn) is available with the same features of the main one. the rf division ratio of this auxiliary output can be set indep endently from the main output in order to increase the flexibilit y. furthermore it is possible to get on the auxiliary output a signal in-phase or in quadratu re with the main one, if the same frequency is selected on both outputs. the auxiliary output st age can also be powered down by software an d/or hardware (pin pd_rf2). the output stage can be muted until the pll ac hieves the lock status; this function can be activated by software.
circuit description STW81200 28/53 docid025943 rev 2 7.11 low power functional mode all the performance characteristics defined in the electrical specifications are achieved in full current mode. the STW81200 is able to provid e a set of low power functional modes which allows control of the current consumption of the different blocks. this feature can be helpful for those applications requiring low power consumption. the power saving modes trade the current cons umption with the phase noise performance, and/or output level. the current of the blocks defined in table 9 can be set by software, and the power saved on each block affect a specific performance as described in the same table. 7.12 STW81200 regi ster programming the STW81200 has 12 registers (10 r/w + 2 read-only) programmed through an spi digital interface. the protocol uses 3 wires (sdi, sck, le) for write mode plus an additional pin (ld_sdo) for read operation. each regist er has 32 bits, one for read/write mode selection, 4 address bits and 27 data bits. figure 19. spi protocol 1. bit for double buffering used for some registers only table 9. blocks with programmable current and related performance block current control bits affected performance vco core 4 bit vco phase noise (offset >pll_bw) vco buffers 2 bit phase noise floor (offset > ~10 mhz) rf dividers core 1 bit/each divider stage phase noise floor (offset > ~10 mhz) rf output stage 3 bit rf output level
docid025943 rev 2 29/53 STW81200 circuit description 52 the data bits are stored in the internal shift register on the rising edge of sck. the first bit ,co is used for mode selection (0=write operation, 1=read operation). the bit a[3:0] represents the register address, and d[26:0] are the data bits. in some registers, the first data bit d26 is used (when set to ?1?) for double-buffering purposes. in this case the register content is stored in a temporary buffer and is transferred to the internal register once a write opera tion is done on the master register st0. figure 20. spi timing diagram table 10. spi timings parameter comments min typ max unit tsetup data to clock setup time 4- -ns thold data to clock hold time 1- -ns tck clock cycle period 20 - - ns tdi disable pulse width 4- -ns tcd clock-to-disable time 1- -ns tec enable-to-clock time 3- -ns
circuit description STW81200 30/53 docid025943 rev 2 7.13 STW81200 re gister summary table 11. spi register map (address 12 to 15 not available) address register name type description page 0x00 st0_register read/write master register. n divider, cp current on page 31 0x01 st1_register read/write double- buffered frac value, rf1 output control on page 32 0x02 st2_register read/write double- buffered mod value, rf2 output control on page 33 0x03 st3_register read/write double- buffered r divider, cp leakage, cp down-split pulse, ref. path selection, device power down on page 34 0x04 st4_register read/write lock det. control, ref. buffer, cp supply mode, vco settings, output power control on page 36 0x05 st5_register read/write low power mode control bit on page 38 0x06 st6_register read/write vco calibrator, manual vco control, dsm settings on page 39 0x07 st7_register read/write fast lock control, ld_sdo settings on page 41 0x08 st8_register read/write ldo voltage regulator settings on page 42 0x09 st9_register read/write reserved (test & initialization bit) on page 43 0x0a st10_register read only vco, lock det. status, ldo status on page 44 0x0b st11_register read only device id on page 45
docid025943 rev 2 31/53 STW81200 circuit description 52 st0 register address: STW81200baseaddress + 0x00 type: r/w description: master register. n divider, cp current 2625242322212019181716 15 14131211109876543210 reserved cp_sel[4:0] pfd_del[1:0] reserved reserved n[16:0] rw rw rw rw rw rw [26] reserved: must be set to ?0? [25:21] cp_sel: set charge pump pulse current value (0 to 4.9 ma; step ~158 a) 00000: (0) set icp=0 00001: (1) set icp=158 a 00010: (2) set icp=316 a ? 11110: (30) set icp=4.74 ma 11111: (31) set icp=4.90 ma [20:19] pfd_del: set pfd anti-backlash delay 00: (0) 1.2 ns (default) 01: (1) 1.9 ns 10: (2) 2.5 ns 11: (3) 3.0 ns [18] reserved: must be set to ?0? [17] reserved: must be set to ?0? [16:0] n: set integer part of n divider ratio (n int ) for n int 512, fractional mode is not allowed (frac and mod settings are ignored)
circuit description STW81200 32/53 docid025943 rev 2 st1 register address: STW81200baseaddress + 0x01 type: r/w applicability: double buffered (based upon dbr bit setting) description: frac value, rf1 output control 26252423222120191817161514131211109876543210 dbr reserved rf1_out_pd rf1_div_sel[2:0] frac[20:0] rw rw rw rw rw [26] dbr: double buffering bit enable; at ?1? the register is buffered and transfe rred only once the master register st0 is written [25] reserved: must be set to ?0? [24] rf1_out_pd: rf1 output power down 0 = rf1 output enabled 1 = rf1 output disabled [23:21] rf1_div_sel: rf1 output divider selection 000: (0) vco direct 001: (1) vco divided by 2 010: (2) vco divided by 4 011: (3) vco divided by 8 100: (4) vco divided by 16 101: (5) vco divided by 32 110: (6) vco divided by 64 111: (7) reserved [20:0] frac: fractional value bit; set the numerator value of the fractional part of the overall division ratio (n=n int +frac/mod) range: 0 to 2097151 (must be < mod)
docid025943 rev 2 33/53 STW81200 circuit description 52 st2 register address: STW81200baseaddress + 0x02 type: r/w applicability: double buffered (based upon dbr bit setting) description: mod value, rf2 output control 26252423222120191817161514131211109876543210 dbr reserved rf2_out_pd rf2_div_sel[2:0] mod[20:0] rw rw rw rw rw [26] dbr: double buffering bit enable; at ?1? the register is buffered and transfe rred only once the master register st0 is written [25] reserved: must be set to ?0? [24] rf2_out_pd: rf2 output power down 0 = rf2 output enabled 1 = rf2 output disabled [23:21] rf2_div_sel: rf2 output divider selection 000: (0) vco direct 001: (1) vco divided by 2 010: (2) vco divided by 4 011: (3) vco divided by 8 100: (4) vco divided by 16 101: (5) vco divided by 32 110: (6) vco divided by 64 111: (7) same divided output of rf1 (not valid if rf1_div_sel=0) [20:0] mod: modulus value bit; set the denominator value of the fractional part of the overall division ratio (n=n int +frac/mod) range: 2 to 2097151
circuit description STW81200 34/53 docid025943 rev 2 st3 register address: STW81200baseaddress + 0x03 type: r/w applicability: double buffered (based upon dbr bit setting) description: r divider, cp leakage, cp down-split pulse , ref. path selection, device power down 262524232221201918171615141312 11 109876543210 dbr pd cp_leak_x2 cp_leak[4:0] cp_leak_dir dnsplit_en pfd_del_mode[1:0] ref_path_sel[1:0] r[12:0] rw rw rw rw rw rw rw rw rw [26] dbr: double buffering bit enable; at ?1? the regist er is buffered and transferred only once the master register st0 is written [25] pd: device power down; at ?1? pu t off all blocks (except ldos) [24] cp_leak_x2: double charge pump leakage current bit 0 = set standard leakage current 1 = set doubled leakage current [23:19] cp_leak: set charge pump leak age current val ue (0 to 620 a; step 10 a or 20 a base upon cp_leak_x2 setting) 00000: (0) set i leak = 0 (default) 00001: (1) set i leak = 10 a (i leak = 20 a if cp_leak_x2 = 1) 00010: (2) set i leak = 20 a (i leak = 40 a if cp_leak_x2 = 1) ? 11110: (30) set i leak = 300 a (i leak = 600 a if cp_leak_x2 = 1) 11111: (31) set i leak = 310 a (i leak = 620 a if cp_leak_x2 = 1) [18] cp_leak_dir: set direction of the leakage current 0: set down-leakage (current sink) 1: set up-leakage (current source) [17] dnsplit_en: at ?1? enables down-split pulse current
docid025943 rev 2 35/53 STW81200 circuit description 52 [16:15] pfd_del_mode: set pfd delay mode; delay val ues set by pfd_del[1:0] in register st0 00: (0) no delay (default) 01: (1) vco_div delayed 10: (2) ref_div delayed 11: (3) reserved [14:13] ref_path_sel: reference clock path selection 00: (0) direct 01: (1) doubled in single mode; not applicable in differential mode 10: (2) divided by 2 11: (3) divided by 4 [13:0] r: set reference clock divider ratio (1 to 8191)
circuit description STW81200 36/53 docid025943 rev 2 st4 register address: STW81200baseaddress + 0x04 type: r/w description: lock det. control, ref. buffer, cp supply mode, vco settings, output power control 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rf_out_pwr[2:0] vco_2v5_mode reserved reserved ext_vco_en vco_amp[3:0] pll_mux_div cp_supply_mode[1:0] kvco_comp_dis pfd_pol ref_buff_mode[1:0] mute_lock_en ld_activelow ld_prec[2:0] ld_count[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [26]reserved: must be set to ?0? [25:23] rf_out_pwr: rf output power control bit; set outp ut power level of differential signal (valid for both rf1 and rf2 outputs; measured @ 4 ghz) 000: (0) -1.0 dbm (-4.0 dbm on each single-ended signal) 001: (1) +1.0 dbm (-2.0 dbm on each single-ended signal) 010: (2) +2.5 dbm (-0.5 dbm on each single-ended signal) 011: (3) +3.5 dbm (+0.5 dbm on each single-ended signal) 100: (4) +4.5 dbm (+1.5 dbm on each single-ended signal) 101: (5) +5.5 dbm (+2.5 dbm on each single-ended signal) 110: (6) +6.5 dbm (+3.5 dbm on each single-ended signal) 111: (7) +7.0 dbm (+4.0 dbm on each single-ended signal) [22]vco_2v5_mode: to be set to ?1? when vco core (pin #3) is supplied at 2.6 v [21]reserved: must be set to ?0? [20]reserved: must be set to ?0? [19] ext_vco_en: external vco buffer enable 0: external vco buffer disabled; integrated vcos are used 1: external vco buffer enabled; external vco required (internal vcos are powered down) [18:15] vco_amp: set vco signal amplitude at the internal oscillator circuit nodes; higher signal level gives best phase noise performance while lower signal level gives low current consumption. different ranges of value are available, ba sed upon the supply voltage provided to pin vcc_vco_core (pin #3). allowed settings: 0000 to 0110: (0-6) when vco core is supplied at 2.6 v 0000 to 1010: (0-10) when vco core is supplied at 3.3 v 0000 to 1111: (0-15) when vco core is supplied at 4.5/5 v [14] pll_mux_div: pll mux setting; select the desi red signal path from vco to the n divider (vco divider in the pll feedback path): 0: vco direct to n divider (default) 1: vco divided to n divider (division ratio set by rf1_div_sel in register st1)
docid025943 rev 2 37/53 STW81200 circuit description 52 [13:12] cp_supply_mode: charge pump supply mode settings; value to be set according to the supply used for charge pump core circuit (pin #16) 00: (0) 4.5v to 5.0 v 01: (1) 3.3 v 10: (2) 2.6 v 11: (3) reserved [11] kvco_comp_dis: disable kvco compensation circuit 0: compensation enabled (default - cp current auto-adjusted to compensate k vco variation) 1: compensation disabled (cp curr ent fixed by cp_sel settings) [10] pfd_pol: set pfd polarity 0: standard mode (default) 1: ?inverted? mode (to be used only with active inverting loop filter or with vco with negative tuning characteristics) [9:8] ref_buff_mode: set reference clock buffer mode 00: (0) reserved 01: (1) differential mode (ref. clock signal on pin #20 and #21) 10: (2) xtal mode (xtal osc. enabled with crystal connected on pin #20 and #21) 11: (3) single ended mode (ref. clock signal on pin #21) [7] mute_lock_en: enables mute function 0: ?mute on unlock? function disabled 1: ?mute on unlock? function enabled (rf output stages are put off when pll is unlocked) [6] ld_activelow: set low state as lock indicator 0: set lock indicator active high (ld=0 means pll unlocked; ld=1 means pll locked) 1: set lock indicator active low (ld=0 means pll locked; ld=1 means pll unlocked) [5:3] ld_prec: set lock detector precision 000: (0) 2 ns (default for integer mode) 001: (1) 4 ns (default for fractional mode) 010: (2) 6 ns 011: (3) 8 ns 100: (4) 10 ns 101: (5) 12 ns 110: (6) 14 ns 111: (7) 16 ns [2:0] ld_count: set lock detector counter for lock condition 000: (0) 4 001: (1) 8 (default for f pfd ~1mhz in integer mode) 010: (2) 16 011: (3) 64 100: (4) 256 101: (5) 1024 (default for f pfd ~50mhz in both fractional/integer mode) 110: (6) 2048 111: (7) 4096
circuit description STW81200 38/53 docid025943 rev 2 st5 register address: STW81200baseaddress + 0x05 type: r/w description: low power mode control bit 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved reserved vco_buff_lp vco_mux_lp rf_div2_lp rf_div4_lp rf_div8_lp rf_div16_lp rf_div32_lp rf_div64_lp rf_div_muxout_lp reserved pll_mux_lp reserved ref_buff_lp rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [26] reserved: must be set to ?0? [25] reserved: must be set to ?0? [24:13] reserved: must be set to ?0? [12] vco_buff_lp: vco buffer low power mode (0=full power; 1=low power) [11] vco_mux_lp: vco mux low power mode (0=full power; 1=low power) [10] rf_div2_lp: rf div. by 2 low power mode (0=full power; 1=low power) [9] rf_div4_lp: rf div. by 4 low power mode (0=full power; 1=low power) [8] rf_div8_lp: rf div. by 8 low power mode (0=full power; 1=low power) [7] rf_div16_lp: rf div. by 16 low power mode (0=full power; 1=low power) [6] rf_div32_lp: rf div. by 32 low power mode (0=full power; 1=low power) [5] rf_div64_lp: rf div. by 64 low power mode (0=full power; 1=low power) [4] rf_div_muxout_lp: rf div. mux low power mode (0=full power; 1=low power) [3] reserved: must be set to ?0? [2] pll_mux_lp: mux pll low power mode (0=full power; 1=low power) [1] reserved: must be set to ?0? [0] ref_buff_lp: ref. buffer low powe r mode (0=full power; 1=low power)
docid025943 rev 2 39/53 STW81200 circuit description 52 st6 register address: STW81200baseaddress + 0x06 type: r/w description: vco calibrator, manual vco control, dsm settings 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dithering cp_up_off cp_dn_off dsm_order[1:0] dsm_clk_disable man_calb_en vco_sel[1:0] vco_word[4:0] cal_temp_comp prchg_del[1:0] cal_acc_en cal_div[8:0] rw rw rw rw rw rw rw rw rw rw rw rw [26] dithering: at ?1? enables di thering of dsm output sequence [25] cp_up_off: for test purposes only; must be set to ?0? [24] cp_dn_off: for test purposes only; must be set to ?0? [23:22] dsm_order: set the order of delta-sigma modulator 00: (0) 3 rd order dsm (recommended) 01: (1) 2 nd order dsm 10: (2) 1 st order dsm 11: (3) 4 th order dsm [21] dsm_clk_disable: for test purpose s only ; must be set to ?0? [20] man_calb_en: enables manual vco calibrator mode 0: automatic vco calibration (vco_ sel, vco_word settings are ignored) 1: manual vco calibration (vco_sel, vco_word settings are used) [19:18] vco_sel: vco selection bit 00: (0) vco_high 01: (1) vco_low 10: (2) vco_mid 11: (3) vco_low [17:13] vco_word: select specific vco sub-band (range:0 to 31) [12] cal_temp_comp: at ?1? enables temp erature compensation for vco cali bration procedure (to be used when pll lock condition is requ ired on extremes thermal cycles)
circuit description STW81200 40/53 docid025943 rev 2 [11:10] prchg_del: set the number of calibration slots for pre-charge of vctrl node at the voltage reference value used during vco calibration procedure 00: (0) 1 slot (default) 01: (1) 2 slots 10: (2) 3 slots 11: (3) 4 slots [9] cal_acc_en: at ?1? increase calibrator accuracy by removing residual error taking 2 additional calibration slots (default = ?0?) [8:0] cal_div: set calibrator clock divider ratio (range:1 to 511); ?0? set the maximum ratio (?511?)
docid025943 rev 2 41/53 STW81200 circuit description 52 st7 register address: STW81200baseaddress + 0x07 type: r/w description: fast lock control, ld_sdo settings 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ld_sdo_tristate ld_sdo_mode spi_data_out_disable ld_sdo_sel[1:0] regdig_ocp_dis cycle_slip_en fstlck_en cp_sel_fl[4:0] fstlck_cnt[12:0] rw rw rw rw rw rw rw rw rw rw [26] reserved: must be set to ?0? [25] ld_sdo_tristate: at ?1? put ld_sdo out pin in tri-state mode [24] ld_sdo_mode: ld_sdo output interface mode selection 0: open drain mode (level range: 1.8v to 3.6v) 1: 2.5v cmos output mode [23] spi_data_out_disable: disable auto-switch of ld_sdo pin during spi read mode 0: ld_sdo pin automatically switched to spi data out line during spi read mode 1: ld_sdo pin fixed to lock detector indication (spi read operation not possible) [22:21] ld_sdo_sel: ld_sdo mux output selection bit 00: (0) lock detector (default) 01: (1) vco divider output (for test purposes only) 10: (2) calibrator vco divider output (for test purposes only) 11: (3) fast lock clock output (for test purposes only) [20] regdig_ocp_dis: for test purposes only ; must be set to ?0? (at ?1? disable the over-current protection of digital ldo voltage regulator) [19] cycle_slip_en: at ?1? enables cycle slip feature [18] fstlck_en: at ?1? enables fast lock mode using pin #6 (pd_rf2/fl_sw) [17:13] cp_sel_fl: set the charge pump current during fast lock time slot (range:0 to 31) [12:0] fstlck_cnt: fast-lock counter value (range: 2 to 819 1); set duration of fast-lock time slot as number of f pfd cycles
circuit description STW81200 42/53 docid025943 rev 2 st8 register address: STW81200baseaddress + 0x08 type: r/w description: ldo voltage regulator settings 2625242322212019181716151413121110987654321 0 pd_rf2_disable reserved reserved reserved reserved reserved reserved reg_ocp_dis reg_dig_pd reg_dig_vout[1:0] reserved reg_ref_pd reg_ref_vout[1:0] reserved reg_rf_pd reg_rf_vout[1:0] reserved reg_vco_pd reg_vco_vout[1:0] reserved reg_vco_4v5_pd reg_vco_4v5_vout[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [26] pd_rf2_disable: at ?1? disable the hardware power down function of the pin pd_rf2 (pin #6) thus allowing the pin pd_rf1 (pin #5) to control th e power down status of both rf output stages [25] reserved: must be set to ?0? [24] reserved: must be set to ?0? [23] reserved: must be set to ?0? [22] reserved: must be set to ?0? [21] reserved: must be set to ?0? [20] reserved: must be set to ?0? [19] reg_ocp_dis: for test purposes only ; must be set to ?0? (at ?1? disable the overcurrent protection of ldo voltage regulators except dig regulator) [18] reg_dig_pd: digital regulator po wer down; must be set to ?0? [17:16] reg_dig_vout: digital regu lator output voltage set 00: (0) 2.6 v (default) 01: (1) 2.3 v (for test purposes only) 10: (2) 2.4 v (for test purposes only) 11: (3) 2.5 v (for test purposes only) [15] reserved: must be set to ?0? [14] reg_ref_pd: reference clock regulato r power down; must be set to ?0? [13:12] reg_ref_vout: reference clock regulator output voltage set 00: (0) 2.6 v (default) 01: (1) 2.5 v (for test purposes only) 10: (2) 2.7 v (for test purposes only) 11: (3) 2.8 v (for test purposes only) [11] reserved: must be set to ?0? [10] reg_rf_pd: rf output section regulat or power down; must be set to ?0?
docid025943 rev 2 43/53 STW81200 circuit description 52 st9 register address: STW81200baseaddress + 0x09 type: r/w description: reserved (test & initialization bit) [9:8] reg_rf_vout: rf output section regulator output voltage set 00: (0) 2.6 v (default) 01: (1) 2.5 v (for test purposes only) 10: (2) 2.7 v (for test purposes only) 11: (3) 2.8 v (for test purposes only) [7] reserved: must be set to ?0? [6] reg_vco_pd: vco bias&control regulator power down; must be set to ?0? [5:4] reg_vco_vout: vco bias&control regulator output voltage set 00: (0) 2.6 v (default) 01: (1) 2.5 v (for test purposes only) 10: (2) 2.7 v (for test purposes only) 11: (3) 2.8 v (for test purposes only) [3] reserved: must be set to ?0? [2] reg_vco_4v5_pd: high voltage regulator power down(to be used to supply vco core, rf output final stage and charge pump); must be set to ?0? [1:0] reg_vco_4v5_vout: high voltage regulator output voltage set (to be used to supply vco core, rf output final stage and charge pump output) 00: (0) 5.0 v (require 5.4 v unregulated voltage line on pin# 36) 01: (1) 2.6 v (3.0-5.4 v unregulated voltage line range allowed on pin#36) 10: (2) 3.3 v (3.6-5.4 v unregulated voltage line range allowed on pin#36) 11: (3) 4.5 v (5.0-5.4 v unregulated voltage line range allowed on pin#36) 26252423222120191817161514131211109876543210 reserved rw [26:0] reserved: test & initializati on bit; must be set to ?0?
circuit description STW81200 44/53 docid025943 rev 2 st10 register address: STW81200baseaddress + 0x0a type: r description: vco, lock det. status, ldo status 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reg_dig_startup reg_ref_startup reg_rf_startup reg_vco_startup reg_vco_4v5_startup reg_dig_ocp reg_ref_ocp reg_rf_ocp reg_vco_ocp reg_vco_4v5_ocp lock_det vco_sel[1:0] word[4:0] r rrrrrrrrrrr r r [26:18] reserved: fixed to ?0? [17] reg_dig_startup: digital regulator ramp-u p indicator (?1? means correct start-up) [16] reg_ref_startup: reference clock regulator ra mp-up indicator (?1? means correct start-up) [15] reg_rf_startup: rf output section regulator ramp-up indicator (?1? means correct start-up) [14] reg_vco_startup: vco bias&control regulator ramp-up indicator (?1? means correct start-up) [13] reg_vco_4v5_startup: high voltage regulator ra mp-up indicator (?1? means correct start-up) [12] reg_dig_ocp: digital regulator ove r-current protection indicator (?1? means over-current detected) [11] reg_ref_ocp: reference clock regulator over-current protection indicator (?1? means over- current detected) [10] reg_rf_ocp: rf output section regulator over-curr ent protection indicator (?1? means over-current detected) [9] reg_vco_ocp: vco bias&control regu lator over-current protection indi cator (?1? means over-current detected) [8] reg_vco_4v5_ocp: high voltage regulator over-curr ent protection indicator (?1? means over-current detected) [7] lock_det: lock detector status bit (?1? means pll locked) [6:5] vco_sel: vco selected by calibration algorithm 00: (0) vco_high 01: (1) vco_low 10: (2) vco_mid 11: (3) vco_low [4:0] word: specific vco sub-band selected by calibration algorithm (range:0 to 31)
docid025943 rev 2 45/53 STW81200 circuit description 52 st11 register address: STW81200baseaddress + 0x0b type: r description: device id 26252423222120191817161514131211109876543210 device_id r [26:0] device_id: device identifier (0x000801c)
circuit description STW81200 46/53 docid025943 rev 2 7.14 power on sequence in order to guarantee the correct start-up of the internal circuitry after the power on, the following steps must be followed: 1. power up the device (ldo supply pins: pin#9 #18, #28 and #36) 2. once the voltages applied on the ldo supply pins are stable, wait 50 msec. (after this transient time, the ldos are powered on with the regulated voltages available at pins #2, #8, #19, #27 and #29, while all other circuits are in power down mode) 3. provide the reference clock signal 4. implement the first programming sequence as follow: a) program register st9 (test & init ialization) with all bit set to ?0? b) program all the remaining registers according to the desired configuration with following order: st8, st7, st6, st5, st4, st3, st2, st1, st0 5. check the pll lock status on pin ld_sdo (pin #26) and/or read all relevant information provided on registers st10 and st11 7.15 example of register programming setup conditions and requirements: ? unregulated supply voltage: 5.0 v ? reference clock: 122.88 mhz , single-ended, sine wave ? lo frequency: 2646.96 mhz ? exact fr eq. mode (vco frequency=5293.92 mhz) ? output power: +7 dbm (differential) ? phase noise requirements: full performance vco; full performance noise floor register configurations (hex va lues including register address) ? st9 = 0x48000000 (initialization; all bit set to ?0?) ? st8 = 0x40000003 (reg_4v5 = 4.5 v) ? st7 = 0x39000000 (?fast lock? not used; ld_sdo pin configured as 2.5 v cmos buffer) ? st6 = 0x30001000 (dithering=0; dsm_order=0 for 3 rd order dsm; cal_temp_comp=1 to guarantee lock on extreme temperature drift) ? st5 = 0x28000000 (low power modes not used) ? st4 = 0x2387838d (lock detector setting for fractional mode and f pfd =61.44 mhz; ref_buf_mode=3 for single-ended mode; vco_amp=15 for best vco phase noise @4.5 v supply; rf_out_pwr=7 to have +7 dbm differential) ? st3 = 0x18000002 (r=2 and ref_path_sel=0 ?direct? for f pfd =61.44 mhz) ? st2 = 0x13000080 (mod=128; rf2_out_pd=1 for rf2 output in power down) ? st1 = 0x08200015 (frac=21; rf1_divsel =1 set rf1 output with vco freq. divided by 2) ? st0 = 0x03e00056 (n int =86; cpsel=31 for icp=4.9 ma)
docid025943 rev 2 47/53 STW81200 application diagram 52 8 application diagram figure 21. application diagram sdi sck hw_pd le ld_sdo pd_rf1 pd_rf2 -controller rf1_outp rf1_outn power supply rf2_outp rf2_outn optional STW81200 icp vctrl fl_sw vcc_cpout vreg_dig vreg_ref vreg_rf vin_ldo_4v5 vin_ldo_ref vin_ldo_rf_dig ref_clkp tcxo ref_clkn rf1_outp rf1_outn rf2_outp rf2_outn vin_ldo_vco vreg_vco cbyp cbyp_4v5 vcc_vco_core vreg_4v5 v reg 4v5 vcc_rfout v reg _ 4v5 vdd_dsm_ndiv v reg _ 4v5 vreg_dig vcc_cp_bias vdd_pfd v reg_ v co v reg_ref vr
application diagram STW81200 48/53 docid025943 rev 2 figure 22. application diagram (external vco) sdi sck hw_pd le ld_sdo pd_rf1 pd_rf2 -controller rf1_outp rf1_outn rf2_outp rf2_outn optiona l STW81200 vcc_cpout vreg_dig vreg_ref vreg_rf ref_clkp tcxo ref_clkn rf1_outp rf1_outn rf2_outp rf2_outn vreg_vco cbyp cbyp_4v5 vcc_vco_core vreg_4v5 v reg 4v5 vcc_rfout v reg _ 4v5 vdd_dsm_ndiv v reg _ 4v5 vreg_dig vcc_cp_bias vdd_pfd v reg_ v co v reg_ref icp extvco_inp extvco_inn out power supply vin_ldo_4v5 vin_ldo_ref vin_ldo_vco vin_ldo_rf_dig vr vctrl
docid025943 rev 2 49/53 STW81200 package mechanical data 52 9 package mechanical data figure 23. package mechanical data
package mechanical data STW81200 50/53 docid025943 rev 2 1. vfqfnp stands for thermally enhanced very thin fi ne pitch quad flat package no lead. very thin: a=1.00 max. 2. details of terminal 1 identifier are optional but must be located on the top surface of the package by using either a mold or marked features. table 12. package dimensions ref. min. typ. max. notes a 0.80 0.90 1.00 a1 0.02 0.05 a2 0.65 1.00 a3 0.20 b 0.18 0.23 0.30 d 5.875 6.00 6.125 d2 1.75 3.70 4.25 e 5.875 6.00 6.125 e2 1.75 3.70 4.25 e 0.45 0.50 0.55 l 0.35 0.55 0.75 k0.25 ddd 0.08
docid025943 rev 2 51/53 STW81200 ecopack? 52 10 ecopack? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark.
revision history STW81200 52/53 docid025943 rev 2 revision history table 13. document revision history date revision changes 21-feb-2014 1 initial release. 07-apr-2014 2 removed ?confidential? banners
docid025943 rev 2 53/53 STW81200 53 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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